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Digital I/O
- IP-Xilinx: (from Dynamic Engineering)
- User programmable Xilinx based IP with xc4005e-2. Two 16 bit wide 1K deep synchronous FIFO memories. 9 RS-485 transceivers. 32 MHz. Bus interface. Support Kit available. Parallel or Serial operation. User frequencies supported
- PMC BiSerial Trans: (from Dynamic Engineering)
- DYNAMIC ENGINEERING's PMC BiSerial family has been updated to include a conduction cooled version with transformer coupling. The PMC-BiSerial-III-TRANS has 8 channels, each fully programmable and capable of operating independently or in concert with the other IO.
Half-Duplex, Full-Duplex, serial and parallel systems can be configured with software and VHDL. The channels are supported by independent state-machines created within the Xilinx FPGA. The channels can have the same or different protocols. Manchester encoding and decoding, standard serial [UART], control, command, instrumentation, and custom protocols can be implemented.
The IO is supported with an advanced PCI interface featuring channelized DMA operation.
The components are rated for the industrial "extended" temperature range. Conformal coating is available.
- PMC Spacewire: (from Dynamic Engineering)
- Utilize SpaceWire to communicate with the European Space Agency and NASA equipment utilizing the ECSS-E-50-12A specification. SpaceWire is configured using routers to create a hierarchical point-to-point system with high speed parallel paths.
The PMC SpaceWire is easy to use. Point and shoot - just fill the FIFO and set the start bit to get your custom protocol transmitting. Built in loop-back capabilities and engineering kits help with integration into your system. Windows driver available. Utilize SpaceWire to communicate with the European Space Agency and NASA equipment utilizing the ECSS-E-50-12A specification. SpaceWire is configured using routers to create a hierarchical point-to-point system with high-speed parallel paths.
http://www.dyneng.com/pmc_SpaceWire.html
- PMC-BiFIFO: (from Dynamic Engineering)
- The parallel Input and Output channels are highly programmable and fully independent. The standard interface offers Data, Clock and Strobe. The 32 RS485 channels are programmable as input or output allowing for a variety of implementations. The programmable output rates and RS422/485 compatability will interface to a multitude of systems.
- PMC-PARALLEL-485: (from Dynamic Engineering)
- 32 differential pairs with direction and termination control for each bit. Simple register based interface. Additional CLK and CLK EN differential pairs. Interrupt generators on 32 IO lines. Custom interfaces welcomed. SCSI III and PN4 IO. Multiple build versions are available. Drivers Available.
- PMC-PARALLEL-IO: (from Dynamic Engineering)
- The PMC-Parallel-IO board adds 64 channels of IO to your carrier board. Each channel is programmable to be input or output on a channel-by-channel basis. Two IO channels can be used as interrupt generators. Interrupts are programmable to be based on level or edge and active high or low. An external clock and clock enable can be used or the internal clock selected for capturing the Input channels. The registers are mapped as 32 bit words and support byte, word and 32 bit access. All registers are read-writeable.
- 2195 -- 32-channel Digital I/O: (from Technobox, Inc.)
- The 32-channel 2195 provides 32-bits of bi-directional CMOS-level (TTL compatible) through its rear I/O connector. Each channel is individually programmed for direction - either input or output - by a 32-bit register written by the host processor. Using programmed I/O via the PCI slave-only bridge, all 32 bits are simultaneously read in parallel, including those bits programmed as outputs. All 32-bits can be written simultaneously in parallel, selectively set, or selectively re-set for those channels programmed as outputs. The state of each digital I/O signal is visible via LEDs located at the PMC front panel.
An additional feature of this board is a 30-ns timestamp. Whenever a change in state occurs on any of the 32-bit digital I/O lines, the hardware detects the change in state and writes all 32-bits into a FIFO, along with a 16-bit timestamp counter.
The timestamp FIFO is accessed via programmed I/O from the PCI bus. The 512 timestamp word storage capacity of the FIFO permits correct capture of closely-spaced digital I/O events. The timestamp FIFO is also written whenever the 16-bit timestamp counter rolls over (i.e., every 2 ms), to maintain timing of infrequently changing digital I/O.
- 2216 -- 192-Channel Digital I/O Subsystem: (from Technobox, Inc.)
- The Technobox 2216 Digital I/O subsystem provides up to 192 points of digital I/O. The subsystem is comprised of a 2216 PMC, cable-attached 82C55-based interface adapters (Technobox P/N 2211), and a differential cable.
Various operational modes permit individual bit set/reset, as well as bi-directional byte-wide transfers with handshake. The 2216 converts the PCI bus into a 1-byte wide differential interface using RS485 signaling levels.
Accesses from the host processor are transferred over the differential interface and are intercepted by 2211 adapter cards that are located remotely on the interface cable. Each 2211 is uniquely addressed by setting a rotary switch on the card and may be placed at any position along the cable. As many as eight (8) 2211s can be installed on the differential cable. Since each adapter card handles 24 digital I/O lines, a total of 192 digital I/O lines for each 2216 PMC card are possible. The twisted pair flat ribbon cable used between the 2216 card and the 2211 adapter cards is a lightweight, non-shielded, flexible PVC-insulated cable which allows convenient routing within a userÕs system. The maximum cable length is 50 feet.
A 50-pin SCSI-style connector on the 2216 front panel provides connection to the differential cable. This scheme makes the 82C55 register set directly visible from the host processor, allowing existing 82C55 software to be readily adaptable to this solution.
Rear I/O may also be supported, using a paddle card to convert the P2 DIN style connector back into the 50-pin SCSI-equivalent required by the differential cable.
Each 2211 adapter card has a 50-pin female, two-row, 0.1" centered header that presents 24 digital I/O signals from the 82C55 (along with a corresponding ground) to the user's hardware. Current source/sink capability for each digital I/O is 2.5 ma.
- 2372 -- 96-Channel FPGA-based Digital I/O: (from Technobox, Inc.)
- The 2372 Reconfigurable Digital I/O PMC which is built around an Altera FLEX 10K Field Programmable Gate Array (FPGA) provides a prototyping vehicle for implementing complex user-specific digital designs.
The EPF10K70RC240-4 is used for the default configuration, which provides the highest gate count at reasonable speeds. For volume production runs, other lower density and/or higher speed parts may be substituted. The design features a total of 96 general-purpose digital I/Os distributed at the front panel (32 I/Os) and at the rear I/O connector (64 I/Os). Each group of eight I/O lines is buffered by a 74FCT16245. The directionality of each group is individually controlled by a user-programmable signal from the Altera FPGA. I/O out the PMC front panel is terminated with an R/C parallel network. By removing its associated capacitor, a line termination circuit can be selectively disabled. Rear I/O is not terminated.
A 128K x 16 SRAM is provided on the PMC and is accessible from the Altera part as well as the PCI interface. A dual-port RAM effect is achieved by arbitrating accesses between the Altera FPGA and PCI bus using control logic implemented in the Altera part. The 16-bit data bus from the PCI slave-only bridge chip, along with 18 address lines (A[17..0]), are connected to the Altera FPGA. 32-bit PCI bus is supported. The PCI bridge will automatically decompose 32-bit PCI accesses into multiple 16-bit equivalents as needed. For application timing, the 33 MHz from the PCI bus and a PLL-generated clock are inputs to the Altera FPGA. Any frequency with better than 0.1% accuracy can be generated by the PLL as programmed from the host processor. Also, two 100-ns delay lines with 5-taps spaced at 20 ns are available for user's time critical asynchronous needs. Finally, two special receivers are available for low-level serial clock and data recovery.
- 2628 -- Multifunction RS422/RS485 Digital I/O: (from Technobox, Inc.)
- The 2628 Multifunction RS422/RS485/Digital I/O board provides the following functions:
One 16550 based UART with RS422 interface.
One 16550 based UART with RS485 interface.
16 bit-oriented Digital I/O as driven by Z8536.
Temperature Sensor.
The two 16550 UARTs on the board provide asynchronous communication at bit rates to 115Kbaud. The 16550's are mapped into host processor space so that standard drivers can be used with the board. Each UART interface provides TXD, RXD, CTS, and RTS control signals. In one case, an RS422 interface with 150 ohm termination is implemented. In the other case, RS485 (multi-drop RS422) is used, with the RTS controlling data direction.
The board also provides a total of 16 general purpose digital I/O lines as driven by one Zilog 8536 Counter/Timer/Parallel I/O chip. Four Z8536 Counter/Timer channels are available on these pins, each providing count input, count output, gate and trigger functions. The digital I/O may be used as bit-oriented inputs or outputs.
Connection to the board is accomplished via a 50-pin SCSI style connector out the front panel. These signals are also routed to the rear I/O connector (PN4) on the PMC, which may be routed out the backplane of a cPCI or VMEbus system for host processors that provide rear I/O connectivity.
Ground and a fuse protected +5V power is provided at the connectors for powering user interfaces. These power lines are alternated with the digital I/O signals in order to reduce cable crosstalk. The PCI bus interface uses a slave-only PLX 9050 part, and the 16550 UARTS and Z8635's are mapped into host processor I/O space via the PCI configuration BAR registers.
A final feature of the board is a temperature sensor for measuring, in 0.5 degree C increments, temperature in the proximity of the PMC module.
- 2674 -- 32-channel Reconfigurable Digitial I/O: (from Technobox, Inc.)
- The 2674 32-channel Reconfigurable RS422/RS485 Digital I/O PMC provides a vehicle for implementing complex user-specific digital designs requiring a differential interface.
At the heart of the 2674 design is an Altera FLEX 10K Field Programmable Gate Array (FPGA. The EPF10K70RC240-4 is used for the default configuration, which provides the highest gate count at reasonable speeds. For volume production runs, other lower density and/or higher speed parts may be substituted.
The design features a total of 32 general-purpose RS422/RS485 driven digital I/Os wired to both the front panel and rear PN4 connector (64 signals per connector taking into account 2 signals per differential pair). The bi-directionality for each of the 32 channels is controlled by an output from the FLEX10K part. The 68-pin front panel connector is compatible with standard fast/wide differential SCSI cables. Furthermore, an optional Technobox transition panel (e.g., P/N 1867) may be used to break out the differential signals into more convenient individual connectors, such as DB9s. Front panel I/O is terminated with parallel resistors. Users can selectively disable line termination by de-populating a line's corresponding resistor.
With the proper ALTERA design the 128K x 32b SRAM provided on the PMC is accessible from the Altera part as well as the PCI interface. The 32-bit data bus is shared between the ALTERA and the PCI interface devices. The SRAM address is driven by ALTERA outputs. This technique allows a variety of memory architectures for the SRAM: single-port SRAM, dualport SRAM, one or more FIFOs, and even linked list structures for more complex applications.
For application timing, the 33 MHz from the PCI bus and a PLL-generated clock are inputs to the Altera FPGA. Any frequency with better than 0.1% accuracy can be generated by the PLL as programmed from the host processor.
On power up, the Altera FPGA configuration cells are automatically loaded from a serial EP
- 2687 -- 2-channel Reconfigurable 155 Mb/s FO: (from Technobox, Inc.)
- A reconfigurable 155 Mb/s Fiber Optic (FO) PMC, the 2687 provides a means for implementing Fiber Optic interfaces for FDDI and other Fiber Optic standards having unusual requirements not supported by standard chipsets. A single transmit channel and a single receive channel each operate at bit rates up to 155 Mb/s. The specific rate can be varied according to a Phase Locked Loop circuit or an on-board 25 MHz crystal. An Advanced Micro Devices FDDI PHY chipset converts the serial bit stream to/from the FO devices to 5-bit wide connections to the ALTERA FPGA. 4b/5b or 8b/10b encoding can be used as implemented in the ALTERA design.
The Fiber Optic interfaces are available out the PMC front panel, and use a standard “ST” style connector. 50 or 62.5 um, 1300 nm multi-mode optical fiber is supported by this product. Also available at the front panel are the PECL equivalents of the serial data stream for the Transmit and Receive Fiber Optic devices, each providing a single differential pair at the MicroD9 connector. Use of either PECL or FO is selected according to the ALTERA design.
- 2979 -- 80-channel Reconfigurable Digital I/O: (from Technobox, Inc.)
- The 2979 80-channel Reconfigurable Digital I/O PMC, which is built around an Altera EPF10K100EQC240-2 Field Programmable Gate Array (FPGA), provides a vehicle for implementing complex user-specific digital designs requiring high-speed, single-ended operation. Sixty-four (64) of the 80 signals are available for rar I/O. All 80 signals are wired to the front panel connector. Each of the 80 signals is directly connected through a 56-ohm series termination resistor to pins on the ALTERA FPGA. Each pin may be an input, output, or bi-directional as determined by the ALTERA design. Using micro-DIP switches on the PMC module, each of the 80 signals may be hard-tied to signal GND in order to accommodate external cabling and connections that require connection to ground.
A PLX Technology 9080 part provides the interface between the PCI bus and the local bus on the PMC. The 9080 has two DMA channels and the ALTERA may request transfer by the corresponding DREQ lines to the 9080. The synchronous pipelined Dual Port memory is a key performance feature of this design. On one side, the dual port memory is accessed from the 9080, and burst transfers are possible using either the 9080Õs DMA or a bursting master on the host processor. The other side of the dual port memory is accessed by the ALTERA through separate pins for the 32-bit Data and 16 address lines.
On power up, the Altera FPGA configuration cells are automatically loaded from a serial EPC2 in-circuit, programmable FLASH memory. If desired, the configuration can be supplied from the host processor or by burning an EPC2 with the userÕs application.
For debug, the upper 16 bits of the 80 I/O lines are available at an optional 20-pin header on the reverse side of the board which mates with a Hewlett Packard logic analyzer probe equipped with a termination adapter.
- 4289 -- Enhanced Reconfigurable RS422/RS485 DIO: (from Technobox, Inc.)
- Reconfigurable platform for implementing complex, user-specific digital designs. Altera CycloneEP1C12F324C8 (approx. 12K LEs). 32-channels (RS422/485) available at both front (68-pin SCSI-type) and PN4 connectors. 256Kx32b SRAM. FPGA configuration can be loaded from EP1CS4 EPROM or host. PLX 9656 PCI bus interface. ICS 1522 PLL provided for controlling application timing (Cyclone also has internal PLLs). Recommended for new application designs.
- ADM-XRC: (from Alpha Data)
- Xilinx Virtex FPGA based PMC card with 34 front panel or 54 rear panel I/O pins. Support for LVTTL, LVDS, LVCMOS and LVPECL I/O standards. 400K to 2000K gate Virtex FPGA for implementation of custom interfaces, 4Mbytes SSRAM, programmable clocks and flash memory for embedded configuration. SDK and wide range of IP Cores available for data pre-processing.
- ADM-XRC-II: (from Alpha Data)
- Xilinx Virtex-II FPGA based PMC card with 146 front panel and 64 rear panel I/O pins. Support for LVTTL, LVDS, LVCMOS and LVPECL I/O standards. 3000K to 10000K gate Virtex FPGA for implementation of custom interfaces, 6Mbytes SSRAM, programmable clocks and flash memory for embedded configuration. SDK and wide range of IP Cores available for data pre-processing.
- ccPMC-Parallel-TTL: (from Dynamic Engineering)
- Conduction Cooled 64 Digital IO or 8 ADC and 32 IO w/ DMA, COS interrupts, PLL
- DPIO2 Digital Parallel PMC: (from Curtiss-Wright Controls, Inc.)
- The DPIO2 is a PCI Mezzanine Card (PMC) designed for high-speed data acquisition and generation. It combines a Digital Parallel Input or Output on one end, and a 64-bit PCI bus master/slave interface with an advanced DMA controller on the other end, with a large FIFO in between. The PCI Interface chip provides a 64-bit PCI bus master/slave interface with a linked list DMA engine. The parallel interface is available through the front panel connector. The logical interface is based on the FPDP protocol. The electrical interface can be TTL (FPDP compliant), RS-422/485, PECL or LVDS, depending on what version of the DPIO2 is used.
- PMC-FPGA05 Virtex-5 LX110 PMC Module: (from Curtiss-Wright Controls, Inc.)
- The PMC-FPGA05 is a Xilinx® Virtex™-5 XC5VLX110 platform FPGA based PMC card with high speed digital I/O and PCI-X interface to the host computer.
There are 138 single-ended I/O lines routed to a 180-way connector near the front panel. These lines are routed so that they may be used as single-ended signals or differential pairs. The FPGA I/O signals are banked, with two banks being used at the front panel connector. Each bank is independently configurable to 2.5V or 3.3V signaling. Developers can create custom I/O modules that utilize these I/O lines using the specifications set out in our documentation that comes with the development card. Another bank of 64 single-ended lines (32 differential pairs) connects to User I/O at the rear of the board, for slower digital communications.
- PMC-HPDI: (from General Standards Corporation)
- A high-speed (40 Mbytes/sec) 16-Bit parallel I/O interface with differential drivers (RS422). Factory configurable to interface to a wide variety of peripherals, custom interfaces, video, digital cameras, other PMC or PCI systems, etc.
- PMC-HPDI32A: (from General Standards Corporation)
- The PMC-HPDI32A board is a fast and flexible bi-directional 32-bit digital I/ O board that transmits and receives data up to 80 Mbytes (differential I/ O) or up to 200 Mbytes (Pseudo ECL I/ O) per second. The board is use-ful as a general-purpose DMA interface to a variety of external peripherals. The PMC DMA engine is capable of transferring data to/from Host memory using D32 block transfers, while the FIFO memory (up to One Mbyte of total FIFO) provides continuous transmission of data without interrupting the DMA transfers or requiring intervention from the Host CPU. The board has 7 bi-directional programmable handshake lines and eight pre-configured software selectable interface protocols to allow easy interfacing to most digital I/ O peripherals.
- PMC-HPDI32A-COS: (from General Standards Corporation)
- The PMC-HPDI32A-COS board is a 32-Bit parallel digital input board that samples input data (via the cable inter-face) at selectable rates. The board can detect any Change-of-State and store the changed data word data in the on-board FIFO. The board is programmable and can generate an interrupt on the first detected change or upon any desired number of changes. Deep FIFO buffers (128 Kbytes) allow data bursts to be transferred over the PCI bus independent of transfers over the cable. Change-Of-State boards allow for more efficient monitoring of peripheral or industrial type devices (transducers, etc.). The board can also be used in a (logic analyzer) type mode by storing up to 64,000 samples after receipt of a trigger word. FIFOs, DMA engine, PCI controller, differential receivers, and multiple status interrupts provides high bandwidth along with complete board control.
- PMC-OPTO-32: (from General Standards Corporation)
- Digital Input/Output, (24 DI, 8 DO), Counter, Timer, high voltage (5 to 48 volts). Opt. high current, optical isolation, debouncing, change-of-state interrupts, programmable handshake
- PMC64-HPDI32ALT: (from General Standards Corporation)
- The PMC64-HPDI32ALT board is a flexible bi-directional 32-bit digital I/ O board that transmits and receives data from 20 Mbytes (TTL I/ O) to 100 Mbytes (LVDS) per second. The board is useful as a general-purpose DMA interface to a variety of external peripherals. The PMC DMA engine is capable of transferring data to/ from Host memory using D32 block transfers, while the FIFO memory (up to One Mbyte of total FIFO) provides continuous transmission of data without interrupting the DMA transfers or requiring intervention from the Host CPU. The board has 7 bi-directional programmable handshake lines and eight preconfigured software selectable interface protocols to allow easy interfacing to most digital I/ O peripherals.
- TPMC600-10: (from TEWS TECHNOLGIES GmbH)
- 32 digital inputs, 24V DC, optically isolated; Fully programmable interrupt capabilities; Electron. Debounce; HD50 SCSI-2 type connector in front panel; Operating temperature -40°C to +85°C
- TPMC600-11: (from TEWS TECHNOLGIES GmbH)
- 16 digital inputs, 24V DC, optically isolated; Fully programmable interrupt capabilities; Electron. Debounce; HD50 SCSI-2 type connector in front panel; Operating temperature -40°C to +85°C
- TPMC600-20: (from TEWS TECHNOLGIES GmbH)
- 32 digital inputs, 24V DC, optically isolated; Fully programmable interrupt capabilities; Electron. Debounce; P14 I/O; Operating temperature -40°C to +85°C
- TPMC600-21: (from TEWS TECHNOLGIES GmbH)
- 16 digital inputs, 24V DC, optically isolated; Fully programmable interrupt capabilities; Electron. Debounce; P14 I/O; Operating temperature -40°C to +85°C
- TPMC630-10: (from TEWS TECHNOLGIES GmbH)
- Reconfigurable FPGA with 64 TTL I/O Lines; PCI Target Controller (PCI9030) with user configurable FPGA (300000 system gates: Xilinx XC2S300E-6); FPGA development tool: Free Xilinx ISE WebPack; FPGA configuration by in system programmable FlashProm via PCI bus; several clock options by programmable clock generator; 64 digital TTL I/O lines; All I/O lines on HD68 SCSI-3 type connector in front panel and on P14; PCI I/O signaling voltage 3.3V and 5V; Operating temperature -40°C to +85°C
- TPMC630-11: (from TEWS TECHNOLGIES GmbH)
- Reconfigurable FPGA with 32 differential I/O Lines; PCI Target Controller (PCI9030) with user configurable FPGA (300000 system gates: Xilinx XC2S300E-6); FPGA development tool: Free Xilinx ISE WebPack; FPGA configuration by in system programmable FlashProm via PCI bus; several clock options by programmable clock generator; 32 differential I/O lines with on board termination; All I/O lines on HD68 SCSI-3 type connector in front panel and on P14; PCI I/O signaling voltage 3.3V and 5V; Operating temperature -40°C to +85°C
- TPMC630-12: (from TEWS TECHNOLGIES GmbH)
- Reconfigurable FPGA with 32 TTL I/O Lines and 16 differential I/O Lines; PCI Target Controller (PCI9030) with user configurable FPGA (300000 system gates: Xilinx XC2S300E-6); FPGA development tool: Free Xilinx ISE WebPack; FPGA configuration by in system programmable FlashProm via PCI bus; several clock options by programmable clock generator; 32 digital TTL I/O lines and 16 differential I/O lines with on board termination; All I/O lines on HD68 SCSI-3 type connector in front panel and on P14; PCI I/O signaling voltage 3.3V and 5V; Operating temperature -40°C to +85°C
- TPMC670-10: (from TEWS TECHNOLGIES GmbH)
- 16 digital inputs, 24V DC, optically isolated, fully programmable interrupt capabilities, electron. Debounce; 16 digital outputs, 24V DC 0.5 A, optically isolated; High side switch; Overload and short circuit protection; HD50 SCSI-2 type connector in front panel; Operating temperature -25°C to +85°C
- TPMC670-11: (from TEWS TECHNOLGIES GmbH)
- 8 digital inputs, 24V DC, optically isolated, fully programmable interrupt capabilities, electron. Debounce; 8 digital outputs, 24V DC 0.5 A, optically isolated; High side switch; Overload and short circuit protection; HD50 SCSI-2 type connector in front panel; Operating temperature -25°C to +85°C
- TPMC670-20: (from TEWS TECHNOLGIES GmbH)
- 16 digital inputs, 24V DC, optically isolated, fully programmable interrupt capabilities, electron. Debounce; 16 digital outputs, 24V DC 0.5 A, optically isolated; High side switch; Overload and short circuit protection; P14 I/O; Operating temperature -25°C to +85°C
- TPMC670-21: (from TEWS TECHNOLGIES GmbH)
- 8 digital inputs, 24V DC, optically isolated, fully programmable interrupt capabilities, electron. Debounce; 8 digital outputs, 24V DC 0.5 A, optically isolated; High side switch; Overload and short circuit protection; P14 I/O; Operating temperature -25°C to +85°C
- TPMC671-10: (from TEWS TECHNOLGIES GmbH)
- 16 Digital Input, 16 Digital Output (High Side Switch); 16 digital inputs, 24V DC, optically isolated to system and to each other, fully programmable interrupt capabilities, electron. Debounce; 16 digital outputs, 24V DC 0.5 A, optically isolated; High side switch; Overload and short circuit protection; HD68 SCSI-3 type connector in front panel; Operating temperature -25°C to +85°C
- TPMC671-11: (from TEWS TECHNOLGIES GmbH)
- 16 Digital Input, 16 Digital Output (Low Side Swich); 16 digital inputs, 24V DC, optically isolated to system and to each other, fully programmable interrupt capabilities, electron. Debounce; 16 digital outputs, 24V DC 0.5 A, optically isolated; Low side switch; Overload and short circuit protection; HD68 SCSI-3 type connector in front panel; Operating temperature -25°C to +85°C
- TPMC671-20: (from TEWS TECHNOLGIES GmbH)
- 16 Digital Input, 16 Digital Output (High Side Swich); 16 digital inputs, 24V DC, optically isolated to system and to each other, fully programmable interrupt capabilities, electron. Debounce; 16 digital outputs, 24V DC 0.5 A, optically isolated; High side switch; Overload and short circuit protection; P14 I/O; Operating temperature -25°C to +85°C
- TPMC671-21: (from TEWS TECHNOLGIES GmbH)
- 16 Digital Input, 16 Digital Output (Low Side Swich); 16 digital inputs, 24V DC, optically isolated to system and to each other, fully programmable interrupt capabilities, electron. Debounce; 16 digital outputs, 24V DC 0.5 A, optically isolated; Low side switch; Overload and short circuit protection; P14 I/O; Operating temperature -25°C to +85°C
- TPMC680-10: (from TEWS TECHNOLGIES GmbH)
- 64-bit TTL I/O; 8 x 8-bit ports; HD68 connector in front panel, 7 of these 8-bit ports available at P14; basic operating modes: byte I/O, 2x16-bit port with handshake, 1x32-bit port with handshake; Interrupt capability; Operating temperature -40°C to +85°C
- TPMC681-10: (from TEWS TECHNOLGIES GmbH)
- 64-bit TTL I/O, Bit I/O; all lines individually programmable as input, output or tri-state; HD68 connector in front panel and P14 I/O, Interrupt capability (rising, falling, both edges) for each I/O line; Operating temperature -40°C to +85°C
- TPMC682-10: (from TEWS TECHNOLGIES GmbH)
- Three 16-bit I/O ports with 512 word FIFO per port and handshake; individually programmable FIFO thresholds; HD68 connector in front panel and P14 I/O, Interrupt capability; Operating temperature -40°C to +85°C
- TPMC700-10: (from TEWS TECHNOLGIES GmbH)
- 32 digital outputs, 24V DC 0.5 A, optically isolated; High side; Overload and short circuit protection; HD50 SCSI-2 type connector in front panel; Operating temperature -25°C to +85°C
- TPMC700-11: (from TEWS TECHNOLGIES GmbH)
- 16 digital outputs, 24V DC 0.5 A, optically isolated; High side; Overload and short circuit protection; HD50 SCSI-2 type connector in front panel; Operating temperature -25°C to +85°C
- TPMC700-20: (from TEWS TECHNOLGIES GmbH)
- 32 digital outputs, 24V DC 0.5 A, optically isolated; High side; Overload and short circuit protection; P14 I/O; Operating temperature -25°C to +85°C
- TPMC700-21: (from TEWS TECHNOLGIES GmbH)
- 16 digital outputs, 24V DC 0.5 A, optically isolated; High side; Overload and short circuit protection; P14 I/O; Operating temperature -25°C to +85°C
- XMC-FPGA05F Virtex-5 FPGA XMC/PMC: (from Curtiss-Wright Controls, Inc.)
- Incorporating quad fiber-optic transceivers with a user programmable Xilinx Virtex-5 FPGA, the XMC-FPGA05F XMC/PMC module combines data processing and I/O in a single module. The FPGA is closely coupled to all interfaces to minimize data bottlenecks.
The XMC-FPGA05F can be used for a wide range of tasks including remote sensor I/O, data recording and linking systems in real-time. The FPGA can be used to implement custom protocols, data encryption or a network processor.
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